1. Field of the Invention
The present invention relates to electronics. More specifically, the present invention relates to comparators and analog to digital converters.
2. Description of the Related Art
Analog to digital converters are widely used for converting analog signals to corresponding digital signals for many electronic circuits. For example, a high resolution, high speed analog to digital converter (ADC) may find application in broadband communications, video circuits, radar, and electronic warfare applications.
The fastest ADC architecture is called “flash” conversion. A flash ADC produces an N-bit digital output in one step using a comparator bank comprised of 2N−1 parallel comparators. Each comparator compares the analog input signal with a different threshold level. The thresholds are typically generated using a resistive ladder or voltage divider. Due to process variables, the multiple resistors of the voltage divider cannot be fabricated to exact values. The voltages generated by the resistive ladder will therefore differ slightly from the desired threshold levels. In addition, the comparators typically also have imperfections, such as imprecise current sources and base currents that affect the resistive ladder. These inaccuracies cause the comparators to change states at the wrong times, generating differential nonlinearity (DNL) and integral nonlinearity (INL) distortions in the system.
A flash ADC may be used by itself, or it may be part of a larger ADC, such as a subranging ADC. In either case, any errors introduced by the flash ADC will propagate through the entire conversion process, creating distortions in the digital output. For a high precision ADC, these errors cannot be tolerated.
The conventional solution to this problem is to trim the resistors of the voltage divider using a large external (hybrid) circuit. The resistive ladder by itself cannot be trimmed to correct any individual threshold because trimming one threshold will affect all the other thresholds. The conventional trimming circuit therefore uses a separate resistor chain for each comparator. This approach utilizes significant surface die area and high power consumption. While this solution achieves the desired accuracies for low resolution (up to about 4–5 bit) ADCs, it is impractically large for larger resolution ADCs. An eight-bit ADC, for example, would need a resistor chain for each of its 255 comparators. Furthermore, this approach is applicable only to single-ended implementations. There is no equivalent approach in the prior art for zeroing errors in a differentially driven comparator bank.
Hence, there is a need in the art for an improved system or method for trimming a flash ADC offering smaller size and lower power consumption than prior art approaches, which is suitable for single-ended or differentially driven high resolution ADCs.